? 2005 fairchild semiconductor corporation ds500056 www.fairchildsemi.com september 1997 revised june 2005 fst16209 18-bit bus exchange switch fst16209 18-bit bus exchange switch general description the fairchild switch fst16209 provides 18-bits of high- speed cmos ttl-compatible bus switching or exchang- ing. the low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. the device operates as a 18-bit bus switch or a 9-bit bus exchanger, which allows data exchange between the four signal ports via the data-select terminals. features 4 : switch connection between two ports. minimal propagation delay through the switch. low l cc . zero bounce in flow-through mode. control inputs compatible with ttl level. ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic diagram truth table connection diagram pin descriptions order number package number package description FST16209MEA ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide fst16209mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide s2 s1 s0 a 1 a 2 function l l l z z disconnect llhb 1 za 1 b 1 lhlb 2 za 1 b 2 lhhzb 1 a 2 b 1 hllzb 2 a 2 b 2 h l h z z disconnect hhlb 1 b 2 a 1 b 1 , a 2 b 2 hhhb 2 b 1 a 1 b 2 , a 2 b 1 pin name description s2, s1, s0 data-select inputs a 1 , a 2 bus a b 1 , b 2 bus b
www.fairchildsemi.com 2 fst16209 absolute maximum ratings (note 1) recommended operating conditions (note 3) note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 3: unused control inputs must be held high or low. they may not float. dc electrical characteristics note 4: typical values are at v cc 5.0v and t a 25 q c note 5: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. supply voltage (v cc ) 0.5v to 7.0v dc switch voltage (v s ) 0.5v to 7.0v dc input voltage (v in )(note 2) 0.5v to 7.0v dc input diode current (l ik ) v in 0v 50ma dc output (i out ) sink current 128ma dc v cc /gnd current (i cc /i gnd ) / 100ma storage temperature range (t stg ) 65 q c to 150 q c power supply operating (v cc ) 4.0v to 5.5v input voltage (v in )0v to 5.5v output voltage (v out )0v to 5.5v input rise and fall time (t r , t f ) switch control input 0ns/v to 5ns/v switch i/o 0ns/v to dc free air operating temperature (t a ) 40 q c to 85 q c symbol parameter v cc (v) t a 40 q c to 85 q c units conditions min typ (note 4) max v ik clamp diode voltage 4.5 1.2 v i in 18ma v ih high level input voltage 4.0 ? 5.5 2.0 v v il low level input voltage 4.0 ? 5.5 0.8 v i i input leakage current 5.5 r 1.0 p a0 d v in d 5.5v 010 p av in 5.5v i off off-state leakage current 5.5 r 1.0 p a0 d a, b d v cc r on switch on resistance 4.5 4 7 : v in 0v, i in 64ma (note 5) 4.5 4 7 : v in 0v, i in 30ma 4.5 8 12 : v in 2.4v, i in 15ma 4.0 14 20 : v in 2.4v, i in 15ma i cc quiescent supply current 5.5 3 p av in v cc or gnd, i out 0 ' i cc increase in i cc per input 5.5 2.5 ma one input at 3.4v other inputs at v cc or gnd
3 www.fairchildsemi.com fst16209 ac electrical characteristics note 6: this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc del ay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). capacitance (note 7) note 7: t a 25 q c, f 1 mhz, capacitance is characterized but not tested. ac loading and waveforms note: input driven by 50 : source terminated in 50 : note: c l includes load and stray capacitance note: input prr 1.0 mhz, t w 500 ns figure 1. ac test circuit figure 2. ac waveforms symbol parameter t a 40 q c to 85 q c, units conditions figure no. c l 50pf, r u r d 500 : v cc 4.5 5.5v v cc 4.0v min max min max t phl , t plh propagation delay bus to bus (note 6) 0.25 0.25 ns v i open figures 1, 2 t phl , t plh propagation delay s to bus 1.5 7.0 7.0 ns v i open figures 1, 2 t pzh , t pzl output enable time, s to a or b 1.5 7.5 8.0 ns v i 7v for t pzl figures 1, 2 v i open for t pzh t phz , t plz output disable time s to a or b 1.0 8.5 9.0 ns v i 7v for t plz figures 1, 2 v i open for t phz symbol parameter typ max units conditions c in control pin input capacitance 3 pf v cc 5.0v c i/o input/output capacitance 10 pf v cc 5.0v, s0, s1, and s2 gnd
www.fairchildsemi.com 4 fst16209 physical dimensions inches (millimeters) unless otherwise noted 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide package number ms48a
physical dimensions inches (millimeters) unless otherwise noted (continued) 5 www.fairchildsemi.com fst16209 18-bit bus exchange switch physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 technology description the fairchild switch family derives from and embodies fairchild ? s proven switch technology used for several years in its 74lvx3l384 (fst3384) bus switch product. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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